In a high-availability system, there is often an architecture whereby some of the subsystems are in use, and some of the subsystems are provided as a backup to the subsystems that are in use. In this configuration, the subsystems that are in use are referred to as ACTIVE, and the subsystems that are for backup purposes are referred to as STANDBY. In such systems, there is a need to provide a distributed method for the delivery of clocking such that an ACTIVE subsystem that may be sourcing a clock to the entire system can be instantaneously switched over to a subsystem that was previously STANDBY, and now takes over as an ACTIVE system. There is typically a requirement that the clock selection be handled by each subsystem which consumes a system clock, and during the switchover, the clock source that is delivered must be glitch-free. Glitch-free clock transition is required in modern electronic systems because a low frequency clock such as 25 Mhz is typically distributed, and thereafter multiplied with phase lock loops (PLLs) up to frequencies as high as 300 Mhz. Since each clock frequency is typically produced by a different PLL on a single subsystem, and each subsystem is expected to retain synchronism, it is a system requirement that the transition from one system clock to another be phase and frequency coherent. When a PLL encounters an extra input transition, or "glitch", the PLL will rapidly increase in frequency, then slow back down to track the system frequency. During this interval, synchronization between the present PLL and the other system PLLs is lost, and this causes data transfers from one clock domain to another to be unreliable.
One prior art system involves selecting a clock between two clock sources, and then following the selected clock with a PLL to smooth out edge discontinuities and glitches that may have occurred during the clock source transition. One such system is described in U.S. Pat. No. 5,260,979 by Parker et al. This type of system works well where there is a single decision point which produces the system clock used by the rest of the system. In applications where the decision point resides on each system card, it is not possible to assure that all of the independent PLLs will track each other at the time of a phase transition following a clock switchover event.
Another prior art system involves the use of three clock oscillators, which self-synchronize to the fastest oscillator and thereafter distribute this signal to the other parts of the system, as described in U.S. Pat. No. 5,553,231. With this system, when the fastest oscillator is removed, the system frequency quickly changes to a slower frequency.
The system of U.S. Pat. No. 5,502,819 generates two asynchronous clocks and distributes each to a clock select circuit which does not change clock selections until the current clock cycle is complete. U.S. Pat. Nos. 4,970,405 and 5,099,140 both similarly blank the new clock until a full cycle of the old clock has completed. This prevents glitches at the point of switchover, but provides for an instantaneous frequency change, since the two clock sources are not locked to each other. Similarly, U.S. Pat. No. 5,502,409 describes a clock selector which synchronizes a "clock switch" signal to the latter-occurring of the two system clocks before switching to the alternate source. U.S. Pat. No. 5,315,181 describes a circuit for selecting between two clocks whereby the select line is synchronized to an output clock formed from a first and second clock. In this system, if the selected input clock were to fail in the 0 or 1 level, the output clock would stop, and the select line would have no further effect.